A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations

This paper proposes a gate-delay model suitable for timing analysis that takes into consideration wideranging process–voltage–temperature (PVT) variations. The proposed model translates an outputcurrent fluctuation due to PVT variations into modifications of the output load and input waveform. After translation, any conventional model can compute delay taking into account PVT variations by using the modified output load and reshaped input waveform. Experimental results with 90and 45-nm technologies demonstrate that the average error of the fall and rise delay estimation in singleand multi-stage gates was approximately 5% on average over a wide range of input slews, output loads, and PVT variations. The proposed model can be used in Monte Carlo STA (static timing analysis) in addition to corner-based timing analysis. It can be also used in statistical STA to calculate the sensitivities of delays to variation parameters on-the-fly even when the nominal operating condition changes as well. & 2013 Elsevier B.V. All rights reserved.